An Extremely Pipelined FPGA-based accelerator of All Adder Neural Networks for On-board Remote Sensing Scene Classification

Directly completing remote sensing scene classification (RSSC) on space platforms can minimize latency and relieve data downlink burdens. The all adder neural network $( \mathrm{A}^{2}$NN) is a novel network for on-board RSSC with lower resource overhead than convolutional neural networks (CNNs). However, most of the existing FPGA-based accelerators are designed for CNNs and are not applicable to deploy $\mathrm{A}^{2}$NNs. In this paper, we propose an extremely pipelined FPGA-based accelerator of $\mathrm{A}^{2}$NNs and implement a VGGNet-11 backbone for on-board RSSC. In the proposed FPGA-based accelerator, an extremely pipelined processing engine (PE) suitable for accelerating the adder layer is designed. Each adder layer in the $\mathrm{A}^{2}$NN is mapped to a dedicated extremely pipelined PE, which achieves low-latency calculations. Besides, the entire parameters of the network are stored in block RAMs, and the intermediate data are cached on the FPGA chip, thereby eliminating external memory accesses and reducing power consumption. To evaluate the performance of the proposed extremely pipelined FPGA-based accelerator of $\mathrm{A}^{2}$NN, we implemented an $\mathrm{A}^{2}$NN-based RSCC model with the VGGNet-11 backbone on the Xilinx Virtex7 XC7VX690T FPGA by the proposed accelerator. The experimental results show that the proposed FPGA-based accelerator of $\mathrm{A}^{2}$NNs can achieve a throughput of 3.04 tera operations per second (TOPs) at 200 MHz while consuming 8.27 W.