A 32-Bit Ripple-Ling Hybrid Carry Adder

The low-order bits of the Ling adder are not on the critical path, eliminating the need for a carry lookahead method to calculate their output sums. In this paper, we propose a hybrid carry adder that combines high-order Ling and low-order ripple techniques. The low 11 bits of the adder utilize a ripple-carry structure, while the high 21 bits employ a Ling-based parallel prefix structure. This approach simplifies the low-order sum circuit without compromising the critical path length of the adder. Furthermore, new intermediate variables are introduced to facilitate Shannon expansion and enable efficient implementation of the output sum. This ensures that the control signal of the output MUX maintains a delay consistent with its input signal. The output sum circuit is further custom designed using reusable logic circuits. The proposed adder is verified using the conventional 180 nm and 28 nm processes, as well as the advanced 14 nm FinFET process, with the layout area as $4557.5 \mu \text{m}^{2}$ , $193.2 \mu \text{m}^{2}$ , and $73.8 \mu \text{m}^{2}$ , respectively. Testing results show that the maximum delay is 0.83 ns, 0.312 ns, and 0.183 ns respectively for the adder using 180 nm, 28 nm, and 14 nm processes respectively. The proposed adder provides an area optimization of approximately 10%~30% and optimizations of 10% in power and speed compared to the conventional Ling adder.