FPGA-based reconfigurable unit for systems identification through RLS algorithm

In order to facilitate the design of classical controllers, modeling functions for unknown control systems is an important goal in control engineering. Therefore, the Recursive Least Squares (RLS) technique is the most recognized method for system identification. In the presented work, the digital architecture of the reprogrammable RLS algorithm for the identification of control systems is proposed, reducing its components by developing the relevant equations for the calculation of the coefficients and minimizing the consumption of resources within a reprogrammable FPGA EP2C20F484C7N board. The proposed embedded system consumes 19% of the logic units and 29% of the multipliers of this device and can also work at a maximum operating frequency of 36.69 MHz.