Junction-Optimized SPAD With 50.6% Peak PDP and 0.64 cps/μm2 DCR at 2 V Excess Bias Voltage in 130 nm CMOS

This letter presents a frontside-illuminated single-photon avalanche diode (SPAD) with high peak photon detection probability (PDP), low dark count rate and low jitter. A retrograde doped and separated deep n-well (DNW) combined with a junction-optimized p-well within the photosensitive region achieves an STI-free structure, significantly minimizing the dark count rate caused by the etching traps and surface states. The visible spectrum’s high PDP is realized through the wide depletion region generated between the carefully modulated p-well and the DNW. Through a globally shared DNW structure, a ${16}\times {8}.{5}\,\,\mu \text{m}$ SPAD array is fabricated and characterized in a 130 nm CMOS process. The measured median breakdown voltage is 16.08 V. The proposed SPAD has a peak PDP of 50.6%, a DCR of 0.64 cps/ $\mu \text{m}^{{2}}$ , an afterpulse probability of 0.16%, and a jitter of 56 ps at an excess bias voltage of 2 V. Therefore, the proposed structure shows excellent potential for time-gated time-of-flight (ToF) and high dynamic range image sensor applications.