Modeling of Bias-Dependent Single Event Transients for Circuit Sensitivity Calculation

The analysis and modeling of Single Event Transients (SETs) generated by particle irradiation in digital integrated circuits (ICs), employ a mixed-mode approach which combines three-dimensional (3-D) semiconductor device simulation with a circuit solver to comprehensively study and understand these effects. In this paper, we present a simpler, more efficient framework to model SETs for estimating the Single Event Upset (SEU) sensitivity at the circuit level using a bias-dependent model. Single-event pulse generation and propagation are simulated and then a calibrated model is created that can be used to compute the circuit vulnerability to SETs in digital logic cells. This methodology is technology agnostic and can reduce SET modeling time significantly. The simulated results have been validated for 180-nm CMOS technology and favorably compared to measured results and full-mixed mode TCAD simulations. The resulting calibrated model can be applied to realistic circuits to estimate single-event vulnerability.