A High-Speed Comparator Using a New Regeneration Latch

This paper presents a high-speed comparator which employs a novel regeneration latch to enhance the comparison process. The regeneration stage employs an innovative mechanism that reduces the RC constant at the output while avoiding static power consumption. Furthermore, the proposed comparator is capable of operating seamlessly with a rail-to-rail input common-mode voltage. This is made possible by utilizing two preamplifiers working in parallel. To partially cancel out kickback noise, the proposed comparator also benefits from an intrinsic neutralization technique. The design was simulated in a 22-nm FD-SOI CMOS technology with a supply voltage of 0.8 V showing that the proposed comparator achieves a 17% decrease in delay compared to the fastest conventional topology simulated in this paper, while consuming the same amount of power.