System-level simulator for the W-CDMA low chip rate TDD system

A system-level simulator for the W-CDMA low chip rate TDD system is developed. This simulator considers multi-cell and multi-user environments and SIR-based power control. For accurate and reliable results, inner-cell and outer-cell interference is modeled by chip-level spreading and an SIR estimation scheme is used. From this simulator, system-level performance is evaluated in terms of the received SIR distributions for downlink and uplink. The degradation probability is also introduced as a QoS indicator at system level.