Gate Robustness and Reliability of P-Gate GaN HEMT Evaluated by a Circuit Method

The small gate overvoltage margin is a key reliability concern of the GaN Schottky-type p-gate high electron mobility transistor (GaN SP-HEMT). Current evaluation of gate reliability in GaN SP-HEMTs relies on either the dc bias stress or pulse I–V method, neither of which resembles the gate voltage (V_GS) overshoot waveform in practical converters. This article develops a new circuit method to characterize the gate robustness and reliability in GaN SP-HEMTs, which features a resonance-like V_GS ringing with pulse width down to 20 ns and an inductive switching concurrently in the drain-source loop. Using this method, the gate's single-pulse failure boundary, i.e., dynamic gate breakdown voltage (BV_DYN), is first obtained under the hard switching (HSW) and drain-source grounded (DSG) conditions. The gate's switching lifetime is then tested under the repetitive V_GS ringing, and the number of switching cycles to failure (SCTF#) is fitted by Weibull or Lognormal distributions. The SCTF# shows a power law relation with the V_GS peak value and little dependence on the switching frequency. More interestingly, the gate's BV_DYN and lifetime are both higher in HSW than those in DSG, as well as at higher temperatures. Such findings, as well as the gate degradation behaviors in a prolonged overvoltage stress test, can be explained by the time-dependent Schottky breakdown mechanism. The gate leakage current is found to be the major precursor of gate degradation. At 125 °C and 100 kHz, the V_GS limits for a 10-year lifetime are projected to be ∼6 V and ∼10 V under the DSG and HSW conditions, respectively. These results provide a new qualification method and reveal new physical insights for gate reliability and robustness in p-gate GaN HEMTs.