A Comparison Study of GaAs E/D-MESFETs Fabricated with Self-Aligned and Non-Self-Aligned Processes

The device characteristics and circuit performance of a self-aligned and a non-self-aligned GaAs E/D-MESFETs have been compared. The fabrication process for the self-aligned MESFETs was similar to the SAINT process [1], with modifications made to enhance yield and to facilitate double-level-metal interconnection. The non-self-aligned MESFETs were fabricated with the conventional recessed-gate process. Electrical measurements across a 2-inch wafer showed that an average self-aligned, 40-µm-wide, 1-μm-long enhancement device has a transconductance of 275 ± 17 mS/mm, a K-value of 16.3 ± 2.7 mS/V, a series resistance of 0.88 ± 0.1 ohm-mm, and a threshold deviation of 28 mV. Corresponding data for the non- self-aligned devices were 191 ± 19 mS/mm, 10.3 ± 1.4 mS/V, 1.2 ± 0.2 ohm-mm, and 45 mV, respectively. A low-power-design ECL-compatible 1-kbit static RAM was fabricated. By using the self-aligned process and a higher depletion threshold, power of the SRAM was reduced from 530 mW for the non-self-aligned SRAM to 220 mW while access times remained the same.