A Self-Aligned Planar GaAs Mesfet Technology for MMICs

A self-aligned gate MESFET technology for high performance and high yield MMICs is described. To reduce the gate resistance, a Ti/Au layer is added onto a WSix refractory gate. An LDD (Lightly Doped Drain) structure is also adopted to increase the gate breakdown voltage and reduce the gate capacitance. Standard deviation of Idss is about 6% over a 2"Φ wafer. In a 0.5µm gate FET, cut-off frequency (fT) of 42GHz and noise figure (NFmin) at 12GHz of 1.25dB are obtained. NFmin less than 1.4dB is obtained with an excellent yield higher than 80%.