A High Yield GaAs Gate Array Technology and Applications

An LSI GaAs gate array consisting of 1224 DCFL gates and 66 I/O buffers has been demonstrated using E/D MESFET technology. The chip dimensions are 4.6 × 43 mm² and it contains 6978 FET's. The key process features are: 1) selective ion-implantation, 2) recessed 1 μιη gates to reduce source-gate parasitic resistance, 3) custom first level interconnect layer and 4) custom airbridge interconnections for second layer metal. The threshold voltages for the Ε-mode and the D-mode FET's are VT = 0.2 V and VP = -0.5 V respectively. The best gm for the Ε-mode FET was measured to be 200 mS/mm. The DCFL gate has a typical propagation delay of 100 ps at 250 μW/gate and the best propagation delay achieved was 52 ps at 550 μW/gate. A pseudo-random sequence generator (140 gates) and an 8-bit serial multiplier (410 gates) have shown yields of 65% and 35% respectively.