Measurement Results for the High Density digitizer System on Chip (HDSoC): A Waveform Digitizer for High Density Detectors

This paper presents measurements of the performance of the first revisions of the HDSoC, a waveform sampling ASIC optimized for high density photo-detectors, such as Silicon Photomultiplier (SiPM) or MA-PMTs. The first revision of HDSoC is operating at 1 Gigasample/sec waveform sampling with the ability to service 32 channels (the second revision is planned to cover 64 channels). The HDSoC is a System-on-Chip with built-in SiPM biasing, input TIA, with internally controlled digitization via a digital core that allows independent operation of each of the channels permitting low latency and high data rate, as well as multiple acquisition modes including dead timeless operation within a rate limit. In this paper we cover extensive test results and plans for future revisions.