Cryogenic Body Bias Effect in DRAM Peripheral and Buried-Channel-Array Transistor for Quantum Computing Applications

This study investigated a novel forward body bias (FBB) analysis to optimize the threshold voltage (
$\text{V}_{\mathrm {th}}$
) at cryogenic temperatures in the latest dynamic random-access memory (DRAM). Electrical measurements were conducted to analyze the cryogenic body bias effect in terms of performance, reliability, and short-channel effect in two types of transistors: DRAM peripheral low
$\text{V}_{\mathrm {th}}$
transistors (Peri LVT) and buried-channel-array transistors (BCAT). At 77 K, the
$\text{V}_{\mathrm {th}}$
shift (
$\Delta \text{V}_{\mathrm {th}}$
) in BCAT was larger than that in Peri LVT due to the difference in channel doping concentration. It was observed that only BCAT experienced a decrease in saturation drain current (
$\text{I}_{\mathrm {d.sat}}$
) at cryogenic temperature because of the large
$\Delta \text{V}_{\mathrm {th}}$
. To compensate for the
$\Delta \text{V}_{\mathrm {th}}$
, FBB was applied to transistors. As a result, FBB effectively controlled the
$\text{V}_{\mathrm {th}}$
and improved carrier mobility. Furthermore, this study demonstrated that FBB reduced hot-carrier degradation (HCD) at cryogenic temperature and improved short-channel effect, such as drain-induced barrier lowering (DIBL). These findings offer valuable solutions for optimizing cryogenic memory operation in quantum computing applications.