Time Controlled Pre-Emphasis Circuit for Broadband Frequency Operation up to 3.6 Gbps

This paper presents a time-controlled pre-emphasis circuit for memory interfaces. At 3.6 Gbps high frequency operation, the eye opening at 1 unit interval (UI) is as small as 50.53%, so to maximize this, adjust the pre-emphasized circuit code to maximize the operating time of the pre-emphasis. However, at a low frequency of 1.2 Gbps, the eye size is large enough at 88% of the 1 UI. This minimizes the pre-emphasizing circuit code to reduce channel power consumption by 5% compared to always operating by pre-emphasizing only high-frequency areas where the signal is transferred or turning off the pre-emphasizing circuit. The proposed design implements in 28 nm CMOS process with 1.2 V supply voltage. The total prototype chip occupies 0.00477 mm².