A High Power Density Gate Driver Integrated SiC Multichip Power Module with Lower Parasitic Inductance

In applications such as multi-electric aircraft, there is an increasing demand for power modules that offer improved volume efficiency and integration. Integration of gate drivers and power semiconductors can reduce the volume of the entire system and reduce the parasitic inductance of the drive circuit, which called intelligent power module(IPM). Consequently, research on high-power intelligent power modules (IPMs) is crucial. However, existing high-power IPMs still suffer from issues such as large physical dimensions and undesirable parasitic inductance. This paper presents a novel approach to address these challenges by introducing a 800V/200A multi-chip parallel intelligent SiC power module with an integrated driver chip. By optimizing the layout of the power loop and the drive loop, a power loop inductance of 7nH and a drive loop inductance of 11.5nH are achieved. Additionally, the warpage of large-size direct bond copper (DBC) substrates is reduced by 36% through the optimization of copper layer thickness, achieving high power density, low parasitic inductance, and enhanced reliability.