Design of Transmission Gate Based SRAM Using Dynamic Modification Scheme

There is a huge need of thousands of kilobytes of computer memory for various applications which can function in the sub-threshold domain. SRAM stands for Static Random Access Memory, and it is made up of flip-flops to store the data. The existing 6T and 8T SRAM cell have their disadvantages like high power consumption, slow access time, and delay. To overcome these limitations, in this project, two design methodologies are implemented. The first design methodology employs a Transmission Gate (TG) for improving SRAM performance. By incorporating TG Logic, the read operation in the SRAM architecture experiences reduced delays, leading to enhanced performance. The second design methodology involves a Power Gating approach. Power gating is a low-power technique in advanced technology standards. Since SRAM plays a critical role in modern computing systems, its security is of utmost importance and the power gating technique will reduce leakage power and decreases latency by more than 80% in comparison with the standard 6T SRAM. The design is implemented in the Tanner EDA (Electronic Design Automation) tool, employing 45nm library files. The laboratory findings highlight the potential of the unique method of boosting SRAM security in computing systems like Internet of Things (IoT) applications.