Seepage Power Aware SBVL Based FinFET Design for SRAM Construction

The main issue in scaling future technology is changes in process parameters, which are seen as flaws in the development process. Devices are also more vulnerable to ageing, temperature fluctuations, and supply voltage variations in their surroundings. Increased power consumption, a lower maximum working frequency, and more failures are all effects of all these impacts that are seen in integrated circuits. With the development of FinFET technology, the unpredictability brought on by random dopant fluctuations has been largely eliminated. Memory makers' top priorities are still power consumption reduction and SRAM cell stability enhancements. The key characteristics of CMOS and FinFET transistors based on SRAM cells are contrasted in this idea. the comparison of self-biased voltage method (SBVL) and sleep transistor simulations of IOT SRAM cell topologies, which are the two main components of the whole process.