A remote partial-reconfigurable SoC with a RISC-V soft processor targeting low-end FPGAs

FPGAs are versatile devices that offer high performance and programmability, making them attractive solutions for diverse applications ranging from edge IoT systems to data center accelerators and beyond. Additionally, partial reconfiguration (PR) is a powerful technique in FPGA design that enables dynamic reconfiguration of specific regions.This paper proposes an FPGA-based SoC that incorporates remote PR and data management capabilities. Moreover, the proposed SoC includes a RISC-V soft processor and leverages TCP communication for remote management and control of the PR process. Its design is intended to be suitable for low-end FPGAs. Besides, since the proposed SoC uses an AXI-Stream interface for communication with the user circuit, the user can easily design and run various circuits using PR. We implement the proposed SoC on the Arty A7-35T FPGA board and verify its functionality using a convolutional neural network (CNN) accelerator operating on the MNIST dataset and a soft processor as an application circuit. The stability and correct operation of TCP/IP communication are confirmed even when the application circuit is frequently reconfigured. We measure the resource utilization and elapsed time needed to configure the application circuit in the proposed SoC. The feasibility evaluation results indicate that the proposed SoC is suitable for real-world use. The number of LUTs, FFs, and BRAMs consumed by the proposed PR controller are reduced to 55%, 24%, and 14%, respectively, compared to previous work, while the throughput is higher than that of a typical JTAG-based configuration.