FPGA Implementation of Area-Time Aware ECC Scalar Multiplication Core*

Elliptic curve cryptography (ECC) is capable of providing higher security per key bit which makes it a great choice for ensuring different security services in many resource-limited environments. Scalar multiplication is the most frequent and performance-limiting primitive required in all security protocols developed using ECC. This paper presents an area-time-aware scalar multiplier architecture and the results are shown after its implementation on different field programmable gate array (FPGA) platforms. It is based on unified finite field arithmetic (UFFA) units, capable of computing basic field operations such as field addition/subtraction, multiplication, and inversion. In these units, efficient parallelism techniques are adopted to increase achievable frequency while novel resource-sharing strategies are employed to reduce the hardware resource consumption cost. Moreover, an efficient scheduling strategy is presented to schedule several field operations required to execute the Montgomery ladder algorithm. Due to these efforts, the proposed scalar multiplier produces better area-time product and efficiency results. It is implemented on Xilinx Virtex-7 and Virtex-6 FPGA platforms for different operand sizes. It provides $3.8 \times$, $3.3 \times$ better results in terms of latency and efficiency as compared to its counterparts.