Bipolar scaling for BiCMOS circuits

The BiCMOS driver of Figure 1 is the most prevalent circuit configuration in BiCMOS circuits. This gate is used in static memories and gale arrays to drive large output capacitors [I-31. It is essential to have a delay model that provides guidelines for the optimum design of the bipolar transistors in these circuits. A simple formula for estimating the delay of the BiCMOS gate is presented in this paper. This formula is verified by simulations from CODECS. a mixed-level circuit and device simulator, using a one dimensional numerical model for the bipolar transistors. SPICE simulations are inadequate since high-level injection effects critical to the performance of the bipolar transistors are not well modeled with present SPICE models. The delay formula and CODECS simulations are used to study the effect IC fabrication technology and supply voltage scaling have on the delay of the gate.