Structure Design of Silicon-Based Nanopore Chips for Noise Reduction

Solid-state nanopores have promising applications in single-molecule detection, including deoxyribonucleic acid (DNA), ribonucleic acid (RNA), proteins, and so on. However, the current noise during nanopore sensor measurement severely limits its detection accuracy. Intrinsic noise of silicon-based chip is a major source of noise for nanopore sensor due to the large chip capacitance. This article systematically studies the influence of chip structure on ionic current noise through a series of experiments and calculations. We design and fabricate SiN–SiO–Si chips with different layer thicknesses, free-standing membrane areas, and selectively thinned areas and measure their noise characteristics. Considering detection sensitivity, noise level, and fabrication cost, the proper structure parameters of chip are given: 1-
$\mu \text{m}$
-thick SiO, 50-nm-thick SiN, and
$20\times 20\,\,\mu \text{m}^{{2}}$
area free-standing SiN membrane with a locally thinned region of diameter less than
$4 \mu \text{m}$
. The biomolecule detection performance of nanopore sensor is evaluated by dsDNA translocation experiments. The signal-to-noise ratios (SNRs) for the nanopore supported by the chip with optimized structure have twice improved.