FastPass: A Fast Pin Access Analysis Framework for Detailed Routability Enhancement

Pin access analysis is a critical step in detailed routing, one of the most complicated stages in the very-large-scale integration (VLSI) physical design flow. In numerous physical design scenarios, where intricate design rules and pin shapes are involved, there is a growing need for efficient and precise evaluation of pin accessibility. Therefore, we introduce FastPass, an improved framework for fast and accurate pin access analysis. FastPass begins by generating pin access routes that adhere to design rules. After that, FastPass preprocesses the conflicts between routes and then employs incremental SAT solving to determine an optimized scheme for pin access. We further integrate FastPass into Dr. CU, a state-of-the-art detailed router to validate its effectiveness. Experimental results on the ISPD 2018 Initial Detailed Routing Contest Benchmark suite show that FastPass can generate design rule checking (DRC)-clean pin access schemes for all cases while being an order of magnitude faster than the known best- acrlong PAAF. With the integration of FastPass, Dr. CU is able to produce detailed routing results with much less short area and fewer DRC violations.