VLSI Architecture for Low Complexity Zero Forcing Equalizer in OTFS Modulation

Orthogonal time frequency space (OTFS) is a promising modulation technique that provides enhanced resilience to time-varying channels, making it suitable for high-mobility scenarios. In this work, we focus on achieving a low-complexity hardware implementation of the zero forcing (ZF) Equalizer for single-input-single-output (SISO) OTFS system. The proposed very large scale integration (VLSI) architecture leverages parallel processing and resource optimization techniques to reduce the computational complexity and hardware requirements of the ZF equalizer. We use the back-to-back connection of fast Fourier transform (FFT) and inverse fast Fourier transform (IFFT) that simplify matrix inversions [1] and it updates without significantly compromising performance. By carefully designing the architecture, we aim to achieve real-time processing capability while meeting are requirements and latency constraints. Through extensive simulations and performance evaluations, we analyze the trade-offs between complexity reduction and equalization performance. Metrics such as bit error rate (BER), latency and area are considered to assess the efficiency and effectiveness of the proposed architecture. We observe from the synthesis results on the 7vx485tffg1157-1 FPGA device that the architecture achieves 440ns latency with 100MHz clock frequency, 249, 843 lookup tables (LUTs) and 74, 611 flip-flops (FF).