Enhancing Transistor Sizing in Analog IC Design using a Circuit-Focused Semi-Supervised Learning

This work investigates the application of artificial neural networks to predict transistor dimensions in analog integrated circuits using semi-supervised learning. Traditionally, circuit designers apply a time-consuming iterative approach to find the optimal dimensions of transistors that satisfy a set of performance metrics. To address this problem, we propose to use artificial neural networks combined with an innovative approach wherein each transistor's dimensions were first predicted using its own network to identify potential learning behavior differences. Some transistors exhibited favorable validation loss levels, while others displayed up to 3 times higher loss values. Building upon this observation, a focused approach was developed, involving the splitting of prediction tasks into two individual networks. The first targeted transistors with low validation losses and relied solely on circuit performance metrics as inputs. The second, designed for challenging transistors, introduced a novel input structure encompassing not only the performance metrics but also the dimensions of other well-trained transistors. This adjustment led to a notable reduction in both training and validation losses by 3.5 times, thus enhancing prediction accuracy for the challenging transistors. These findings underscore the importance of tailored artificial neural networks in enabling more efficient transistor sizing and present a promising approach for advancing analog integrated circuit design automation. Furthermore, this study contributes to the understanding of machine learning efficiency in the context of analog design.