A Resource-efficient FIR Filter Design Based on an RAG Improved Algorithm

In modern digital filter chip design, efficient resource utilization is a hot topic. Due to linear phase characteristics of FIR filters, a pulsed fully parallel structure can be applied to attack the problem. In order to further reduce hardware resource consumption especially caused by multiplication function, an improved RAG algorithm is proposed. Filters with different orders and for different algorithms are compared, and the experimental results show that the improved RAG algorithm is excellent in terms of logic resource utilization, resource allocation, running speed, and power consumption under different application scenarios. The proposed algorithm invokes a better circuit structure for FIR filter, it gives full play to resource allocation strategy and reduces logic resource consumption. The proposed circuit is faster and more stable, and suitable for a variety of complex application scenarios.