A 25-Gb/s 3-D Direct Bond Silicon Photonic Receiver in 12-nm FinFET

This letter presents a 25-Gb/s 3D-integrated optical receiver, which consists of an electronic integrated circuit (EIC) die fabricated in 12-nm FinFET technology and a photonic integrated circuit (PIC) die fabricated in AIM Photonics’ integrated photonic technology. EIC is flip-chip bonded to PIC through direct bond interconnect (DBI), allowing for significantly reduced parasitic. Except for reduced input-referred noise thanks to improvements in PIC and packaging, variable bandwidth transimpedance amplifier (TIA) with multistage feedback amplifier is utilized for further noise reduction and front-end bandwidth compensation for better full-link energy efficiency. This TIA is followed by a broadband amplifier with active inductor loading, dc cancellation loop, RC LPF generating the pseudo-differential signal, 4 quarter-rate slicers, and a 4-to-8 de-serializer. Measurements demonstrate −17.0-dBm optical modulation amplitude (OMA) sensitivity at 25 Gb/s with 2.12-mW receiver power and 2.66-mW receiver clocking power, which translates to 191.2 and 84.8 fJ/bit receiver energy efficiency, with and without per-channel injection-locked oscillator (ILO) power. Each receiver channel occupies
$1560 \mu {}\text{m} ^{\mathrm{ 2}}$
. To the author’s best knowledge, it is the best OMA sensitivity, energy efficiency, and silicon area simultaneously achieved among published 25 Gb/s optical receivers.