Nanosheet Count Optimization Strategy of Complementary FET (CFET) Scaling Beyond 2 nm From Device to Circuit

Complementary Field-Effect Transistors is one of the most promising structures for replacing GAA (Gate-All-Around) field-effect transistors while continuing the advancement of Moore's Law. Thus, optimizing its structure is a crucial research direction. This study proposes a nano-sheet count design strategy to address the issue of mismatched electron and hole mobilities in standard CFET cell and a nine-stage ring oscillator (RO). The simulation results demonstrate the effective matching of electron and hole mobilities by adjusting the ratio of NMOS (n-type) and PMOS (p-type) nano-sheet counts, thus enabling the optimization of circuit performance and power consumption for specific applications. In the CFET of the RO unit, a frequency increase of 10% and a capacitance reduction of 6% are achieved with only a 3% increase in power consumption, comparing a CFET with four P-doped nano-sheet channels and two N -doped nano-sheet channels to one with three P-doped nano-sheet channels and three N-doped nano-sheet channels.