Design of Millimeter-Wave Asymmetric Single-Pole Double-Throw Switch in a 45nm SOI CMOS Technology

An asymmetric single-pole double-throw (SPDT) switch in a 45-nm silicon-on-insulator (SOI) CMOS process is presented for 5G millimeter-wave (mm-wave) applications. The LC resonant technique and L-/ π -type topology are used to achieve a low insertion loss of less than 0.9 dB in the on-state path and a high isolation of more than 25 dB in the off-state path for 20-34 GHz. At 27 GHz, the 0.1 dB input power compression point for TX and RX paths is 29.1 and 21.0 dBm, respectively. The overall size area of the designed SPDT switch is 0.84 mm * 0.34 mm.