Efficiency and Speed Trade-Offs in 8-Bit CMOS Adders at 180nm: An In-Depth Examination

This paper analyses the performance of different adders in terms of power delay and area. Adders are fundamental units in arithmetic circuits. Adders, till now, have undergone several modifications to improve its efficiency. Advancement of adders is necessary for enhancement of complex circuits in which they are employed. The most important parameters that determine the performance effectiveness of an adder are area, power dissipation and delay. Choosing the finest adder with the required properties is crucial to upgrade the performance of the circuits in which its application has a significant effect. This paper compares twelve 8-bit adders based on the abovementioned performance parameters, thus reducing the hectic task of selecting the proper adder. All these adders are implemented using CMOS logic. Simulation of these adders has been done using Cadence Virtuoso tool in 180nm technology. Power, delay and area values of all these adders are tabulated in this paper. Based on the results obtained from the comparison, it has been observed that 8-bit 14T full adder consumed the least power, carry skip adder exhibits the least delay and the adder which occupies the least area in terms of transistor count is 8T full adder. This paper helps to identify the adder which gives the best performance in 180nm technology node in terms of power, delay and area.