Implementation and Analysis of Single Digit BCD Multipliers Without Generating Partial Products

Multipliers play a crucial role in signal processing systems and any improvement in their speed directly enhances the overall system performance. Traditionally, multipliers consist of two main components: partial product generation and addition of these partial products to obtain the final results. Binary-coded decimal (BCD) multipliers additionally require a binary to BCD conversion step to achieve the desired output. Performance enhancement of multipliers can be done by reducing the number of partial products formed or by using compression techniques to reduce the number of bits to be added. Fast adders with reduced propagation delays can also be utilised. While using faster binary multipliers for BCD multiplication, binary to BCD converters are needed. The converters add more delay to the multiplier circuit. The proposed multipliers do away with the need for both partial product generation and its addition along with binary to BCD converters. By eliminating the need for partial product generation and addition, the proposed multiplier achieves notable speed improvements. The multiplier uses Vin-culum method for bit reduction. The multiplier is implemented on Basys3 board using Xilinx Vivado 2020.2. When implemented on Artix-7 FPGA, the multiplier showed a speed improvement of 53 % compared to BCD multiplier using traditional array multiplier and BCD converter