Performance Evaluation of Adder Architectures for Vedic Multiplier Implementation

Performance evaluation of adder architectures for Vedic multiplier implementation is introduced in this article. The purpose is to evaluate and analyze various adder architectures inside the Vedic multiplier’s area, power, latency, and performance characteristics. The adder architectures examined Carry Skip adders (CSKA), Ripple Carry adders (RCA), Kogge Stone adders (KSA), Brent Kung adders (BKA), and Compressor adders. To minimize the number of adders needed, this article examines the use of specialized compressors, which can process multiple bits simultaneously. The proposed adder architecture uses the Urdhva Tiryakbhyam algorithm from Vedic mathematics to enhance the multipliers’ performance on area and speed. In the Vedic multiplier, power consumption has been proven to be affected by the type of adder used, stressing the need to select an appropriate adder design. FPGA implementation using Virtex2 XC2V40-6cs144 board, which provides a reliable and accurate platform for performance analysis, is used for experimental assessment. According to the analysis, the compressor adder uses 33.3% fewer slices, 37.5% fewer LUTs, and has a gate count of 45.8% lower than the other adder architectures. The findings of this article are useful in determining the most efficient and appropriate adder architecture for Vedic multiplier implementation.