Low-Power and Area-Efficient M-Term Binary Polynomial Multiplier for Finite Field

The complexity of multipliers used to generate large random keys in cryptographic systems contributes to the complexity of the entire cryptographic system, hence making it essential to design multipliers with low complexities. In addition to the complexity reduction, low-power consumption and highspeed are two major demands in any VLSI circuit design. In this case, a Composite Multiplier that combines the advantages of the Karatsuba multiplication algorithm and the Schoolbook multiplication algorithm is helpful because it is area and time efficient. This paper proposes further modification to the existing Composite multiplier [12] and comparing it to the same concerning various parameters like area, power, delay, and area-delay-product (ADP). In the recombination stage of the proposed multiplier, the ripple carry adder is replaced by a Kogge Stone adder. With this modification, there is a 65.9% decrease in the delay, a 1.14% increase in the area, a 14.35% decrease in power, and a 65.5% decrease in the area-delay-product (ADP) as compared to the existing design. Then, a counter is added just before the Kogge-stone adder. The counter counts the number of 1’s in each column of the partial product to eliminate the addition process if all the bits of a particular column are 0. This counter helped to reduce the number of additions required in the recombination stage of the Karatsuba algorithm. This proposed multiplier showed a 6.6% decrease in area, a 66% decrease in delay, an 18.2% decrease in power, and a 66% decrease in ADP in comparison with the ripple carry adder-based multiplier. Further, the Kogge-stone adder is replaced by multiple adders with a counter, which led to a 14% decrease in area and a 57.4% decrease in power. Verilog HDL is used to write the RTL code for all the circuits. All the circuits are simulated using Xilinx ISE and are synthesized on the Cadence Genus RTL synthesis tool (90 nm Technology).