FPGA based realization of a High-Speed 8-Tap FIR Filter for Signal Processing Applications

Memory-based technology is widely used in various applications of digital signal processing. Compared to other accumulation structures, memory-based structures offer advantages in terms of space and power minimization. Additionally, the access time for memory-based structures is faster than traditional multiplication methods. In the case of the FIR filter, Look-Up Tables (LUTs) are commonly used for performing MultiplyAccumulate (MAC) calculations. This paper proposes a novel approach where the LUT of the FIR filter incorporates the anti-symmetric product coding (APC) and odd-multiple-storage (OMS) techniques, specifically designed for 10 bit signed input and coefficients, to improve the performance of the system. By partitioning the LUT using the APC and OMS approaches, the utilization of the LUT is significantly reduced, resulting in improved power efficiency. This combination of techniques reduces the LUT usage to one fourth compared to traditional FIR-based LUTs. The designed system focuses on a 10-bit signed Finite Impulse Response (FIR) filter. FIR filters are commonly used for frequency selective filtering, noise reduction, and signal amplification in digital signal processing applications. The proposed filter operates on 10-bit signed data, allowing for a wider dynamic range and improved accuracy compared to filters with smaller bit-depths.Here also validating the proposed design with the moving avarage FIR filter.