Phase Frequency Detector using PLL for High Frequencies

The dawn of 5G communication technology marks a pivotal moment in the evolution of our interconnected world. With its arrival, a sweeping transformation is underway, characterized by a substantial increase in operating frequencies that promises to redefine the boundaries of connectivity. In view of this situation, our paper details the design and working of a linear, spike-free Phase Frequency Detector (PFD), which is a component utilized within a Phase-Locked Loop (PLL) arrangement tailored to operate efficiently at elevated frequencies. Two spike-free PFD models are proposed in this report. The first model uses a reset circuit to prevent both error signals from simultaneously going high and a set of inverters to eliminate spikes in the output signal, while the second model builds on the first model with a set of 2-to-1 multiplexers to further minimize spikes and logically select the output signal for the next block of the PLL. The PFDs were found to have an input range of -2$\pi$ to 2$\pi$, a maximum operating frequency of 900 MHz at 2.2V; the PLL with the PFD was found to have a lock-time of 2.80 microseconds and a unity gain frequency of 700.28 MHz.