A Proposal for Optimization of Spacer Engineering at Sub-5-nm Technology Node for JL-TreeFET: A Device to Circuit Level Implementation

This article for the first time explores the effect of different spacer materials on junctionless (JL) TreeFET for the IRDS sub-5-nm technology node. The study focuses on evaluating the influence of various spacer materials (Air, SiO2, Si3N4, Al2O3, HfO2, and TiO2) on dc and analog/RF performance, considering both single-
${k}$
and dual-
${k}$
spacer materials while maintaining a fixed
${L}_{\text {g}}$
= 8 nm and spacer lengths (
${L}_{\text {ext}}$
= 5 and 7 nm). The single-
${k}$
spacer analysis demonstrated better dc performances with
${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$
, subthreshold swing (SS), and drain-induced barrier lowering (DIBL)
$\sim > 10^{{8}}$
, ~61 mV/dec, and ~63 mV/V, respectively, at
${L}_{\text {ext}}=7$
nm, for the TiO2 spacer. The analog parameters
${A}_{\text {V}}$
, gain frequency product (GFP), and gain transconductance frequency product (GTFP) experienced significant improvements of ~58.7%, ~70.9%, and ~55.95% for the TiO2 spacer at 10-nA normalized drain current. However, the RF parameters, such as
${f}_{\text {T}}$
and
${f}_{\text {MAX}}$
, tend to be deteriorated by an amount of ~64.5% and ~62.6%, respectively. To further optimize the device performance, four dual-
${k}$
spacer configurations (HfO2 + Air, HfO2 + SiO2, TiO2 + Air, and TiO2 + SiO2) are explored. Specifically, by employing an inner high-
${k}$
spacer length (
${L}_{\text {sp},\textit {hk}}{)}$
of
${L}_{\text {ext}}$
/2, notable enhancements are achieved in
${A}_{\text {V}}$
,
${f}_{\text {T}}$
,
${f}_{\text {MAX}}$
, GFP, and GTFP by ~69.5%, ~17.5%, ~27.4%, ~37.7%, and ~36.06%, respectively, making TiO2 + Air dual-
${k}$
spacer suitable for analog/RF applications. The dc performance is also found to be best for this combination too as compared with all other combinations. Particularly, when decreasing
${L}_{\text {sp},\textit {hk}}$
from
${L}_{\text {ext}}$
/2 to
${L}_{\text {ext}}$
/6, the dc, and analog/RF performances are found to be degraded. Furthermore, the best-optimized device (TiO2+ Air) when implemented to design a CMOS inverter circuit, a voltage gain of ~12 V/V and a delay of 5.32 ps is achieved. Overall, this article pioneers the incorporation of spacer analysis in JL-TreeFET, unveiling its potential for pushing the boundaries of performance and efficiency in modern semiconductor devices.