Design of the Main Control RISC-V Processor in Chiplet Applications

The method of bootloader for multi-chip systems on chiplet are interesting topics to approach goals of low power and high performance. Meanwhile, designers find the complexity of multi-stage boot in heterogeneous SoCs being a challenge. To boot the multiple chips, a SPI2AHB Master module is designed. The module allows adjacent chips to function as either slave or master in the heterogeneous SoCs and enables the rewriting of SRAM to ensure the system can start up properly. The communication between the main control module and dedicated processor units is realized through the co-share memory with interrupt handshaking, effectively avoiding memory consistency issues. The paper chooses the SiFive E21, based on the RISC-V instruction set as the main control processor, to design a heterogeneous SoC system with the chiplet technology. The implementation of each component, and the corresponding test benches, are written using Verilog HDL in RTL. The project produced the RISC-V main control processor is loaded into Cyclone IV FPGA for system verification. The results show the heterogeneous SoC system can successfully boot in two different boot methods, SRAM and flash while maintaining very low resource utilization on FPGA.