Research On Thermal Simulation Analysis Of Chip-on-film

As the current of integrated circuits (ICs) gradually increase within the high-performance application, power consumption also increases, which in turn raises the overall temperature of the ICs. To make sure these high-power consumption chips could operate within a certain temperature range. The thermal managements on chips are becoming increasingly important. This research aims to discuss the thermal impact of Chip-on-Film (COF) packages on the temperature of chips. This study develops a simulation model to simulate the junction temperature of IC and analyze the temperature distribution profile in COF package. The complete mechanical COF package design is imported into a simulation software for thermal analysis. Each mechanical COF package design corresponds to varying Inner Lead Bonding (ILB) trace design. It means that each IC in different application product requirements corresponds to a different ILB trace design on each COF package. This study implements the different ILB layout designs on COF package and transfers these ILB trace layout from two-dimension file into three- dimensional simulation model. By generating three-dimensional structures, they can be imported into ANSYS thermal software to simulate the junction temperature of IC and temperature profile on total COF package for each ILB trace design. The heat transfer is enhanced by optimizing the ILB trace routing on the COF package to reduce the IC temperature. Furthermore, infrared thermometers will be used to measure the temperature of IC on different COFs, and the results will be compared with the simulation results. Based on results, the design of different trace routing on the COF package has an impact on IC temperature. The optimized ILB trace design can effectively reduce the junction temperature of IC. This study shows the results that the design of ILB trace contact(B) is more helpful than the design of ILB trace w/o contact(A) for improving IC temperature performance. In addition to optimizing the design of ILB traces, attaching heatsink on the COF package is also an effective method for reducing junction temperature of IC. In the current application, the heatsinks could be attached to the top side and to the bottom side of COF package. The size of the heatsinks are vary depending on the specific application requirements. By using the same method, this study also generates two different sizes of heatsinks in common within dimensions of 26mmx12mm and 30mmx15mm and simulate the junction temperature of IC to evaluate to temperature reduce on IC. These two heatsinks are attached separately to the top side and bottom side in simulation model. By developing the three-dimensional model in thermal analysis, we could get the junction n temperature of IC at first and evaluate the various feasibility of thermal management.