Clock Network Design Challenges

Clock network makes a large contribution to overall power consumption due to the large number of interconnects and frequent switching of clock elements. Developing a reliable, high-performance, low-power clock network is becoming increasingly difficult as technological design standards become increasingly tighter. To ensure the reliability of the circuit, it is necessary to use restrictions that affect the complexity of timing closure. The structure of this article is as follows: in Chapter II, a literary analysis of dissertations on the topic of clock network design was carried out and the problems that were considered in them were presented in Chapter III definitions of clock network design indicators were given, which most often become objects of scientific research; Chapter IV presents methods used in clock network design, such as: 1) Clock gating; 2) Clustering; 4) Changing the size of library elements; 6) Use of various clock network architectures: h-tree, clock mesh, clock tree with cross links tree, clock tree, clock spine; 7) Hybrid methods. The result provides the research community with a brief overview of the challenges associated with clock network design techniques and presents the overall picture of clock network design to guide future research in the right direction.