Real-Time Feature Extraction for Readout ASICs: Algorithms and On-Chip Implementations

Recent work has proposed the integration of machine learning (ML) algorithms within the front-end ASICs used for charge detection and readout in high-energy and nuclear physics experiments. The main goal is to alleviate data transfer bottlenecks to back-end FPGAs by only transmitting higher-level signal features. The latter may either be continuous-valued (e.g., amplitude, time constant, time of arrival) or discrete (e.g., particle ID). Several types of artificial neural networks (ANNs), such as multi-layer perceptrons (MLPs) and convolutional NNs (CNNs), have been optimized for this purpose. However, the performance of such networks on noisy data has not been compared with either fundamental accuracy limits (from estimation theory) or more conventional algorithms.This paper seeks to fill the gap by 1) deriving theoretical performance bounds; 2) comparing the performance of a variety of algorithms against these bounds; and 3) implementing the selected algorithms on-chip using high-level synthesis (HLS) tools. To this end, the paper derives theoretical error bounds for estimation of higher-level features from digitized waveform data. The performance of several algorithms, including matched filters, nonlinear recursive filters (NRF), nonlinear least squares (NLS), and ANNs, is compared with these bounds for an amplitude estimation task. Additional algorithms are developed and evaluated for 1) estimation of pulse shape parameters, and 2) pulse shape classification. An automated design flow is developed for implementing hardware-optimized versions of the algorithms in real-time on front-end ASICs starting from high-level code in MATLAB. Synthesis results in 65 nm CMOS technology are also presented.