A FPGA implementation of Resonance Demodulation and its Spectrum Analysis

Nowadays, the real-time performance of fault diagnosis is not high enough, hardware methods can be adopted, including using DSP processor or field programmable gate array (FPGA). many scholars have deployed DL and ANN algorithms on FPGA to achieve fault diagnosis, so it is more meaningful and challenging to preprocess the signal with the help of digital circuit and implement the traditional resonance demodulation algorithm in hardware. This algorithm is realized by a digital circuit with FIR filter, multiplier and square root module. In terms of FFT the real-time mode and non-real-time mode are compared. Compared with the previous resonance demodulation algorithms, the characteristic frequency error obtained is less than 1Hz. The research shows that deploying the traditional resonance demodulation algorithm on FPGA can make the system have strong versatility and maneuverability.