Accelerators in Embedded Systems for Machine Learning: A RISCV View

Embedded systems, which are mobile systems with IoT and constrained processing capability, have mostly functioned as a depiction of ubiquitous computing throughout the previous ten years. On the other hand, innovative applications are expanding, consuming more data, and employing ever-complicated algorithms. To run complex algorithms, accelerators have been added into the normal architecture of embedded systems made for convolutional neural networks (CNN), a machine learning technique. Energy economy, adaptability, versatility, and heterogeneity are some characteristics that the new devices that handle ML in embedded applications must have. However, ML algorithms cannot be executed on embedded systems because to a lack of computational capacity. To compute CNN model inference, accelerators are recommended and integrated into the embedded system utilizing the same energy and resource-saving methods. The appeal of accelerators based on the RISC-V architecture is the possibility to deliberately alter the host processor to improve communication with the accelerator. This work seeks a balanced design between acceleration and flexibility to deploy several CNN model configurations.