A Low-Power Cyclic Vernier Time-to-Digital Converter for In Pixel Applications

In this paper, a low power cyclic vernier time-to-digital converter (TDC) with a tunable resolution is presented. The structure which includes two ring oscillators performs measurement in three stages of coarse stage, medium stage, and fine stage. The fine stage achieves high accuracy measurement through the use of two ring oscillators. The medium stage measurement is obtained by counting the period of the higher frequency oscillator and using the period difference of two oscillators, and the coarse stage measurement is obtained by counting the period of the lower frequency oscillator. The structure uses a controller circuit that at the end of the measurement, turns off the ring oscillators to reduce power consumption. The proposed TDC is simulated in 65nm CMOS technology. Its resolution is 20ps, its average power consumption is $\mathbf{320}\boldsymbol{\mu}\mathbf{W}$, and its area is $\mathbf{52}\times \mathbf{52}\boldsymbol{\mu} \mathbf{m}^{\mathbf{2}}$.