Temperature Dependence of Critical Charge and Collected Charge in 5-nm FinFET SRAM

Single-port (SP) and two-port (TP) static random access memory (SRAM) arrays in a commercial 5-nm FinFET technology were exposed to alpha particles at ambient and elevated temperatures up to 100 °C. Results show that increasing operating temperatures of these devices leads to significant changes in single-event upset (SEU) cross sections and multicell upset rates. Technology computer-aided design (TCAD) simulations are used to investigate the changes in charge collection and its relationship with changes in restoring current to affect storage node susceptibility. Simulations show that diffusion charge collection increases significantly for low LET particles incident outside drain regions of storage nodes. However, increasing drive current with temperature for FinFET transistors leads to decreasing SEU cross section for temperatures rising from 25 °C to 75 °C. Differences in charge collection and capacitance between SP and TP cell designs lead to decreasing SEU cross section for SP cells and increasing cross section for TP cells as temperature increases to 100 °C. These changes in vulnerability may lead to inaccurate predictions from accelerated testing at ambient temperatures if real operational temperatures are different.