An Anti-Removal-Attack Hardware Watermarking Method Based on Polymorphic Gates

Watermarking is an effective way to protect the intellectual properties (IPs) of hardware. The polymorphic gate based watermarking technique was recently proposed where certain standard logic gates are replaced by polymorphic gates to embed watermarks. However, the special structure of the polymorphic gates makes them distinguishable from the standard logic gates. It enables the attacker to discover the watermarks after reverse engineering, and to remove them by replacing the polymorphic gates with the functional equivalent standard cells. The proposed polymorphic watermarking method enhances the hardware watermarks against the removal attacks by reducing the IP's quality once the watermark is removed. To reach this goal, the specific Satisfiability Don't Care (SDC) conditions in the netlist are identified, and they are utilized to define the polymorphism that results in more cost on delay, power and area after the removal attack. Additionally, an observability don't care (ODC) based technique is introduced to increase the number of gates with the required SDC conditions to accommodate the long watermark bits. Furthermore, the trap gate technique is introduced to avoid the polymorphic gates being replaced back with the original gates. The simulation results on ISCAS‘85 and MCNC benchmark circuits show that the average overhead in circuit delay, area and power of the proposed method are only 3.97%, 4.75% and 3.26% respectively to embed 128-bit watermarks compared with the original circuits, but become 92.80%, 70.32% and 53.55%, respectively after removal attacks.