Local Layout Effect-Aware Static Timing Analysis by use of a New Sensitivity-Based Library

This paper presents a method for accurately accounting for Local Layout Effect (LLE) in Static Timing Analysis (STA). Conventional timing analysis methodologies often add timing margins at the block level to account for LLE, despite its predictable nature, due to the challenges of integrating local effects into conventional STA flow. The proposed method addresses this challenge by incorporating detailed layout information into the timing analysis, which accurately models LLE. The resulting approach reduces timing margins, improving the performance of designs while maintaining accuracy. The proposed methodology extracts physical layout parameters and converts them to threshold voltage and mobility shift, which are then used to adjust the timing of the circuit. This adjustment is made by referring to a characterized delay sensitivity table. Compared to traditional methodologies that use timing margins, the proposed methodology significantly reduces pessimism, allowing for more optimization opportunities. The cost of this approach is only a small increase in the characterization cost, making it a cost-effective solution. The proposed methodology has been successfully applied in practice to analyze and optimize designs under timing effects induced near RX width transitions. The results showed an improvement of around 2.6% in the maximum frequency and a 6% reduction in leakage power. This highlights the effectiveness of the proposed approach in achieving better design optimization while maintaining accurate timing analysis.