MapBuf: Simultaneous Technology Mapping and Buffer Insertion for HLS Performance Optimization

Buffer placement (i.e., pipelining) for frequency regulation is a fundamental step of high-level synthesis (HLS). Typical HLS approaches place buffers before technology mapping; as the circuit implementation details are unknown, the HLS tool must resort to precharacterized and conservative delay estimates when deciding on the buffer placement. An alternative is to place buffers after technology mapping when the circuit details are known. However, the buffers themselves may invalidate prior mapping assumptions and irreversibly impact the ultimate circuit frequency. In this work, we propose a methodology that simultaneously tackles technology mapping and buffer insertion in HLS-produced dataflow circuits. The source code of our approach is open-source and integrated into a complete HLS framework; it achieves a 13.32% and 11.14% average improvement in execution time and area compared to state-of-the-art approaches that handle buffering and technology mapping separately.