FPGA Implementation and Architecture Design of Polar Encoder for 5G-NR

This work focuses on the FPGA implementation of the 3GPP complaint polar encoder for 5G-new radio (NR). We use Xilinx's polar intellectual property (IP) aka polar IP for the polar encoding functionality. We design a polar configuration IP by generating the bit allocation (BA) table, configuring register values and passing the right control parameters. Next, a parameter handler is developed which is a memory mapped module and provides an advanced extensible interface (AXI)-lite interface to the polar IP. To test the functionality of the polar IP, a Verilog test bench is developed. It provides configuration parameters, payload and BA table in compliance with 3GPP standards to the polar configuration IP. We verify the output of our implementation with the Matlab 5G-NR built-in library on the Xilinx evaluation board. Our results show the efficiency of the implementation in terms of latency and resource utilization on the evaluation board.