Challenges for designing an FPGA-based data link layer processor dedicated to sub-THz communication

This paper discusses the challenges of implementing beam management algorithms, forward error correction, automatic repeat request, data aggregation, and data fragmentation in a state-of-the-art field programmable gate arrays (FPGA) platform considering wireless communication in the sub-THz band at frequencies between 100 GHz and 300 GHz. A data link layer architecture is proposed, which supports the processing of the data frames directly in the FPGA logic for reduced latency, while the beam management is delegated to a software processor. This approach can significantly simplify data link layer processor implementation and improve efficiency.