Design and Characterization of 6T SRAM bitcell using 18nm FinFET

The number of memory instances per chip is rapidly growing, with some estimates predicting that memories and other extensive macros would occupy more than 90% of the die space within five years. SoC designers are increasingly concerned about memory characterization since they want accurate and efficient models at all phases of the design process. The sheer quantity and severity of the difficulties are escalating the situation.SRAM is the most used type of memory for high- speed and small-area applications. Its main feature is that it can retain the data stored in the bitcell as long as it is powered up, unlike a DRAM cell where the data is stored in a capacitor. Various kinds of bitcells are used in the construction of SRAM, such as 4T, 6T, 8T, and 10T (T: Transistor). Among those, the 6- Transistor bitcell is most widely used due to its symmetric circuit and its packing efficiency.In this paper, we have implemented 6T bitcell in 18nm FinFET technology. We have designed three types of bitcells: High- Density, High-Current and High-Performance bitcells. Several characterization metrics such as Read Current, Leakage current, Write Margin, Static Noise Margin, Retention Noise Margin, and power dissipation have been examined and compared for various voltage and temperature variations.