Modular Design Architecture of a HPEC System

The current High Performance Embedded Computing (HPEC) platform is an embedded server based on VITA VPX Standards. It is a 3/4-ATR system with 4-slots based on VPX VITA 46 standards in 3U form factor. It has two independent SBCs based on Intel Xeon-D and Xeon-E series, a GPGPU module based on Nvidia and an IO card for MIL-1553 and ARINC applications. The design of such a complex system meeting the performance, size, thermal and EMI/EMC challenges is a herculean task in its own right. In addition to these common challenges in such a system, the current paper discusses about efforts to make the system modular to ensure faster time to market for different variants. In addition, the high TFLOPS performance of such systems make them ideal for AI applications.